Semiconductor structure and method for forming same

ABSTRACT

Embodiments of this application provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: a first substrate is provided; the back surface of the first substrate is etched to form a trench; a conductive layer is formed in the trench; a first conductive column that extends into the trench is formed at a back surface of the first substrate; a device layer is formed at a front surface of the first substrate, and the device layer includes a storage array and a contact structure; and a second conductive column that penetrates through the device layer and extends into the first substrate is formed; the first conductive column is electrically connected with the second conductive column through the conductive layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a U.S. continuation application ofInternational Application No. PCT/CN2021/107199, filed on Jul. 19, 2021,which claims priority to Chinese Patent Application No. 202110790535.3,filed on Jul. 13, 2021. International Application No. PCT/CN2021/107199and Chinese Patent Application No. 202110790535.3 are incorporatedherein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to, but is not limited to, asemiconductor structure and a method for forming the same.

BACKGROUND

With the development of semiconductor technologies, the characteristicsize of an integrated circuit is continuously reduced, and theinterconnection density of devices is continuously increased. In orderto reach devices with high density, better performance and a loweroverall cost, technicians have developed a series of advanced packagingtechnology. A three-dimensional packaging technology, which has betterelectrical properties, higher reliability and ability of achievinghigher packaging destiny, is widely applied to various high-speedcircuits and miniaturized systems. A through-silicon via (TSV)technology is a new technology for stacking chips to forminterconnections in a three-dimensional integrated circuit, where manyvertically interconnected TSV structures are manufactured on a siliconwafer to achieve electrical interconnections among different chips. TheTSV technology allows the maximum density of the chips stacked in athree-dimensional direction, the shortest interconnecting line among thechips, and the smallest overall size. Moreover, the chip speed and thelow power consumption performance are greatly improved. The TSVtechnology is currently the most remarkable technology among electronicpackaging technologies.

However, since the TSV structure has a greater depth-to-width ratio, theTSV structure will not work if a problem occurs to any one of an etchingprocess, a filling process and an aligning process.

SUMMARY

According to a first aspect, embodiments of this application provide amethod for forming a semiconductor structure. The method includes thefollowing operations.

A first substrate is provided.

A back surface of the first substrate is etched to form a trench.

A conductive layer is formed in the trench.

A first conductive column that extends into the trench is formed at theback surface of the first substrate.

A device layer is formed at a front surface of the first substrate, andthe device layer includes a storage array and a contact structure.

A second conductive column that penetrates through the device layer andextends into the first substrate is formed.

The second conductive column is electrically connected with the firstconductive column through the conductive layer.

According to a second aspect, embodiments of the application provide asemiconductor structure. The semiconductor structure includes asubstrate, a device layer and a TSV. The device layer is located at afront surface of the substrate.

The TSV is arranged in the substrate and penetrates through thesubstrate and the device layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, unless otherwise specified, the same reference numeralsthrough drawings indicate the same or similar parts or elements. Thedrawings are not necessarily drawn to scale. It should be understoodthat the drawings only describe some implementation modes of thisapplication, and should not be regarded as limiting the scope of thisapplication.

FIG. 1 is a flowchart schematic diagram of a method for forming a TSVstructure according to embodiments of this application.

FIG. 2A to FIG. 2N are local sectional schematic diagrams of a formingprocess of a TSV structure according to one embodiment of thisapplication.

FIG. 3 is a sectional schematic diagram of a semiconductor structureaccording to embodiments of this application.

DETAILED DESCRIPTION

The following clearly and completely describes the exemplaryimplementation modes of this application with reference to theaccompanying drawings. Although the drawings show exemplaryimplementation modes of this application, it should be understood thatthis application can be implemented in various forms and shall not belimited by implementation modes described herein. In fact, theseimplementation modes are provided to understand this applicationthoroughly, and completely convey the scope of this application toperson skilled in the art.

A number of specific details are given below to provide a more thoroughunderstanding of this application. However, it is apparent to personskilled in the art that this application can be implemented without oneor more of these details. In other examples, to avoid confusion withthis application, some technical features known in the art are notdescribed; namely, not all the features of the actual embodiments aredescribed here. Known functions and structures are not described indetail.

In addition, the drawings are schematic diagrams of this applicationonly and are not necessarily drawn to scale. The same reference numeralin the drawing indicates the same or similar part, so their repeateddescription will be omitted. Some of the block diagrams shown in thedrawings are functional entities, and do not necessarily correspond tophysically or logically independent entities. These functional entitiesmay be implemented in software form, or in one or more hardware modulesor integrated circuits, or in different network and/or processor devicesand/or microcontroller devices.

The flowchart shown in the drawings is an exemplary description only anddoes not necessarily include all the steps. For example, some steps mayalso be decomposed, while some steps may be merged or partially merged,so the order of actual execution may be changed according to the actualsituation.

It should be understood that spatially relational terms such as “under”,“beneath”, “lower”, “below”, “above”, and “upper” may be used herein forconvenience of description to describe a relationship between oneelement or feature and another illustrated in the figures. It is to beunderstood that, in addition to the orientation shown in the figures,the spatially relational terms are intended to further include differentorientations of devices in use and operation. For example, if thedevices in the figures are turned over, elements or features describedas being “beneath” or “below” or “under” other elements or features willbe oriented to be “on” the other elements or features. Therefore, theexemplary terms “beneath” and “under” may include both above and below.The device may be additionally oriented (rotated by 90 degrees or inother orientations) and the spatial descriptors used herein may beinterpreted accordingly.

The terms used herein are for the purpose of describing specificembodiments only and not intended to limit the disclosure. As usedherein, singular forms “a/an”, “one”, and “the” are also intended toinclude the plural forms, unless otherwise specified in the context. Itis also to be understood that, when the terms “comprising” and/or“including” are used in this specification, the presence of thefeatures, integers, steps, operations, elements, and/or components isdetermined, but the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groups is alsopossible. As used herein, the term “and/or” includes any and allcombinations of the related listed items.

Embodiments of this application provide a method for forming asemiconductor structure. FIG. 1 is a flowchart schematic diagram of amethod for forming a semiconductor structure according to embodiments ofthis application. As shown in FIG. 1 , the method mainly includes thefollowing operations.

At S110, a first substrate is provided.

At S120, the back surface of the first substrate is etched to form atrench. A conductive layer is formed in the trench.

In embodiments of this application, the first substrate is provided.Herein, the first substrate may be a semiconductor substrate. Thesemiconductor substrate may be an elemental semiconductor materialsubstrate (for example, a silicon (Si) substrate, a germanium (Ge)substrate, etc.), a composite semiconductor material substrate (forexample, a silicon-germanium (SiGe) substrate), or a silicon oninsulator (SOI) substrate and a germanium on insulator (GeOI) substrate,etc.

In embodiments of this application, before S120, the back surface of thefirst substrate may also be subjected to chemical mechanical polishing(CMP) treatment, so as to thin the first substrate. For example, thethickness of the first substrate is ground to 50-70 μm. In an actualapplication, the thinning thickness of the first substrate may beadjusted according to the actual needs.

In embodiments of this application, a first insulation layer, a firstdiffusion barrier layer and a copper thin film layer are successivelydeposited in the trench. The copper thin film layer located at thebottom of the trench forms the conductive layer. A second diffusionbarrier layer is deposited in the trench. The second diffusion barrierlayer covers the copper thin film layer. An insulation material isfilled in the trench to form an insulation filling layer. The insulationfilling layer covers the second diffusion barrier layer.

FIG. 2A to FIG. 2N are local sectional schematic diagrams of a formingprocess for a semiconductor structure according to one embodiment ofthis application. The method for forming the semiconductor structure ofthe embodiment of this application is described below in combinationwith FIG. 1 and FIG. 2A to FIG. 2N.

In the embodiment of this application, as shown in FIG. 2A, aphotoetching glue layer 202 is formed at the back surface of the firstsubstrate 201. The photoetching glue layer 202 is exposed and developedto obtain photoetching glue layer 202 that is patterned. Thephotoetching glue layer 202 that is patterned has a first opening 203.In a specific embodiment, the first opening may be a circular opening,and the diameter of the circular opening is 10-30 μm. It needs to benoted that the first opening may be an opening with other shapes, forexample, an elliptical opening, a square opening and the like, theapplication is not limited thereto.

The first substrate 201 is etched by taking the photoetching glue layer202 that is patterned as a mask, so as to form the trench 204. Afterthat, the photoetching glue layer 202 is removed, and the formedstructure is as shown in FIG. 2B. In some embodiments, after removingthe photoetching glue layer 202 that is patterned, the formed structuremay be washed, so as to remove the etching residue. In an actualapplication, the first substrate may be etched for example by a dryetching process. In a specific embodiment, the etching depth of thetrench 204 may be 30-50 μm. In an actual application, the etchingthickness of the trench can be adjusted according to the actual needs.

In embodiments of this application, the depth of the trench is equal tohalf of the thickness of the first substrate.

The first insulation layer 205, the first diffusion barrier layer 206and the copper thin film layer 207 are successively deposited in thetrench. The copper thin film layer located at the bottom of the trenchforms the conductive layer 2071. In a specific embodiment, the thicknessof the conductive layer 2071 may be 700-1000 nm. In an actualapplication, the thickness of the conductive layer may be adjustedaccording to the actual needs.

In one embodiment, the first insulation layer 205 may be formed in thetrench by an atomic layer deposition (ALD) process. The material of thefirst insulation layer 205 includes, but is not limited to at least oneof SiO₂, Si₃N₄ or low dielectric constant material. The first diffusionbarrier layer 206 is formed on the first insulation layer 205 by aphysical vapor deposition (PVD) process. The material of the firstdiffusion barrier layer 206 includes, but is not limited to at least oneof TaN, Ta, ZrN or Cu. The copper thin film layer 207 is formed on thefirst diffusion barrier layer 206 by an electroplating process.

In some embodiments, when forming the copper thin film layer 207, anaccelerator and an inhibitor may be added in the electroplating processto control the deposition rate, so that the copper thin film layer 207is formed at the bottom and top of the trench, while less copper thinfilm layer is deposited at the side wall of the trench. In a specificexample, the accelerator may be polyalkylene glycol, and the inhibitormay be organic sulfide. In some embodiments, the copper thin film layerdeposited at the side wall of the trench may also be removed through dryetching, and only the copper thin film layer at the bottom of the top ofthe trench is reserved.

After performing the above deposition, the formed structure is as shownin FIG. 2C.

A second diffusion barrier layer 208 is deposited in the trench. Aninsulation material is filled in the trench to form an insulationfilling layer 209, and the formed structure is as shown in FIG. 2D. Insome embodiments, the second diffusion barrier layer is deposited by theALD process. The material of the second diffusion barrier layerincludes, but is not limited to at least one of SiN, TaN or Tia. Theinsulation filling layer is formed in the trench by a Chemical VaporDeposition (CVD) process. The material of the insulation filling layerincludes, but is not limited to at least one of SiO₂, Si₃N₄ or lowdielectric constant material.

Herein, a trench structure includes the first insulation layer 205, thefirst diffusion barrier layer 206, the copper thin film layer 207, thesecond diffusion barrier layer 208 and the insulation filling layer 209.The copper thin film layer at the bottom of the trench forms theconductive layer 2071.

The material of the first insulation layer 205 may be the same as thatof the insulation filling layer 209.

At S130, a first conductive column that extends into the trench isformed at the back surface of the first substrate.

As shown in FIG. 2E, a first photomask layer 210 that is patterned isformed, and the first photomask layer 210 that is patterned is providedwith a second opening 211. In a specific embodiment, the second openingmay be a circular opening, and the diameter of the circular opening is7-10 μm. It needs to be noted that the second opening may be an openingwith other shapes, for example, an elliptical opening, a square openingand the like, the application is not limited thereto.

The insulation filling layer 209 and the second diffusion barrier layer208 is etched by taking the first photomask layer 210 that is patternedincluding the second opening a mask, to form a first blind hole 212.After forming the first blind hole 212, the first photomask layer 210that is patterned is removed, and the formed structure is as shown inFIG. 2F. Herein, the first blind hole 212 exposes part of the conductivelayer 2071. When forming the first blind hole 212 by etching, theconductive layer 2071 may be used as an etching stopping layer. Theetching of the first blind hole stops at the copper thin film layer 207by controlling the etching selection ratio, so that the first blind holepenetrates through the insulation filling layer 209 and the seconddiffusion barrier layer 208 to expose part of the conductive layer 2071.

As shown in FIG. 2G, a third diffusion barrier layer 213 is deposited inthe first blind hole 212, and the third diffusion barrier layer 213covers the side of the first blind hole 212 and exposes part of theconductive layer 2071. A first metal material 214 is filled in the firstblind hole, and the first metal material 214 covers the third diffusionbarrier layer 213. In some embodiments, the third diffusion barrierlayer 213 is deposited in the first blind hole by the PVD process, andthe material of the third diffusion barrier layer includes, but is notlimited to at least one of TaN, Ta, ZrN or Cu. The first metal material214 is filled in the first blind hole by the electroplating process, andthe first metal material includes, but is not limited to at least one ofcopper or tungsten.

The material of the third diffusion barrier layer 213 may be the same asthat of the first diffusion barrier layer 206. The material of the firstmetal material 214 may be the same as that of the copper thin film layer207.

As shown in FIG. 2G, the chemical mechanical polishing process isperformed at the back surface of the first substrate, so that the topsurface of the first conductive column is flush with that of thesubstrate, and the formed structure is as shown in FIG. 2H. The firstsubstrate may also be thinned from the back surface of the firstsubstrate through the above chemical mechanical polishing process, andthe thickness of the first substrate may be ground to 40-60 μm. In anactual application, the thinning thickness of the first substrate may beadjusted according to the actual needs.

In combination with FIG. 2A to FIG. 2H, namely, the first conductivecolumn 215 extending into the first substrate 201 is formed at the backsurface of the first substrate 201. The first conductive column 215 isformed in the trench structure and electrically connected with theconductive layer 2071 at the bottom of the trench.

As shown in FIG. 2H, the third diffusion barrier layer 213 in the firstconductive column 215 contacts with the conductive layer 2071 throughthe opening of the second diffusion barrier layer 208 at the bottom ofthe trench, so that the first metal material 214 filled in the firstconductive column 215 is electrically connected with the conductivelayer 2071 through the third diffusion barrier layer 213.

At S140, the device layer is formed on the front surface of the firstsubstrate, and the device layer includes a storage array and a contactstructure.

As shown in FIG. 2I, the structure as shown in FIG. 2H is overturned, sothat the front surface of the first substrate 201 is upwards.

As shown in FIG. 2J, the device layer 216 is formed on the front surfaceof the first substrate 201, and the device layer 216 includes thestorage array 217 and the contact structure 218. The storage array 217may include structures such as an active area, a word line, a bit lineand a capacitance. The contact structure 218 may include a conductivecontact structure and a metal layer that are formed on the storage array217, and is configured to lead out the storage array. For example, thecontact structure 218 may be configured to control the signaltransmission of one or more source electrodes and/or drain electrodes,the word line, and the bit line in the active area. In this embodiment,the contact structure 218 is formed in the insulation layer.

In a specific example, the contact structure 218 may include aperipheral contact structure formed on the storage array 217, a metallayer electrically connected to the peripheral contact structure and aconductive contact structure electrically connected to the metal layer.Herein, the metal layer is located between the peripheral contactstructure and the conductive contact structure.

At S150, the second conductive column that penetrates through the devicelayer and extends into the first substrate is formed, and the secondconductive column is electrically connected with the first conductivecolumn through the conductive layer.

In the embodiment of this application, as shown in FIG. 2K, a secondphotomask layer 219 that is patterned is formed, and the secondphotomask layer 219 that is patterned is provided with a third opening220. In a specific embodiment, the third opening may be a circularopening, and the diameter of the circular opening is 7 μm. It needs tobe noted that the third opening may be an opening with other shapes, forexample, an elliptical opening, a square opening and the like, theapplication is not limited thereto.

As shown in FIG. 2L, the device layer 216 and the first substrate 201 isetched by taking the second photomask layer 219 that is patternedincluding the third opening as a mask, to form a second blind hole 221.After forming the second blind hole 221, the second photomask layer 219that is patterned is removed, and the second blind hole 221 exposes partof the conductive layer 2071. The conductive layer 2071 is used as anetching stopping layer, and the second blind hole 221 is formed byetching. By controlling the etching selection ratio, the second blindhole penetrates through the device layer 216, the first insulation layer205 and the first diffusion barrier layer 206, and exposes part of theconductive layer 2071.

In some embodiments, the opening size of the first blind hole is thesame as or different from that of the second blind hole as long as thatthe opening size of the first blind hole and the opening size of thesecond blind hole are less than the width (along a horizontal directionof the first substrate) of the conductive layer 2071.

As shown in FIG. 2M, the second insulation layer 222 is deposited in thesecond blind hole 221, and the second insulation layer 222 at the bottomof the second blind hole is removed by etching. A fourth diffusionbarrier layer 223 is deposited in the second blind hole and the secondmetal material 224 is filled in the second blind hole, so as to form thesecond conductive column 225. Herein, the second insulation layer isdeposited in the trench by the ALD process, and the material of thesecond insulation layer includes, but is not limited to at least one ofSiO₂, Si₃N₄ or low dielectric constant material. The fourth diffusionbarrier layer is deposited on the second insulation by the PVD process,and the material of the fourth diffusion barrier layer includes, but isnot limited to at least one of TaN, Ta, ZrN or Cu. The second metalmaterial is filled in the first blind hole through the electroplatingprocess, and the material of the second metal material includes, but isnot limited to at least one of copper or tungsten.

The material of the second insulation layer 222 may be the same as thatof the first insulation layer 205. The material of the fourth diffusionbarrier layer 223 may be the same as that of the third diffusion barrierlayer 213. The material of the second metal material 224 is the same asthat of the first metal material 214.

In the embodiments of this application, the fourth diffusion barrierlayer 223 in the second conductive column 225 contacts with theconductive layer 2071 through at the opening the second insulation layer222 at the bottom of the second blind hole, so that the second metalmaterial 224 filled in the second conductive column 225 is electricallyconnected to the conductive layer 2071 through the fourth diffusionbarrier layer 223.

In the embodiments of this application, the second conductive column 225is electrically connected with the first conductive column 215 throughthe conductive layer 2071 at the bottom of the trench.

The chemical mechanical polishing process is performed on the structureas shown in FIG. 2M, so that the second conductive column is flattenedfrom the front surface of the first substrate 201, and the top surfaceof the second conductive column 225 is flush with that of the devicelayer 216. The formed TSV structure is as shown in FIG. 2N.

As shown in FIG. 2N, the TSV structure includes the first conductivecolumn 215, the second conductive column 225 and the conductive layer2071 that are electrically connected to each other. The TSV structure iscross-shaped. The widths of the first conductive column 215 and thesecond conductive column 225 are gradually reduced in a directionperpendicular to and towards the conductive layer 2071.

Thus, in the embodiments of this application, the first conductivecolumn 215 is formed in the trench structure, and the first conductivecolumn 215 is electrically connected with the second conductive column225 through the conductive layer 2071. In a direction parallel to thesubstrate, the width of the conductive layer 2071 is greater than thatof the contact surface of the first conductive column 215 and theconductive layer 2071 and that of the contact surface of the secondconductive column 225 and the conductive layer 2071, so that when thesecond conductive column 225 is formed at the front surface of the firstsubstrate, it only needs to contact with the conductive layer 2071. Inother words, the projections of the first conductive column 215 and thesecond conductive column 225 on the conductive layer 2071 are notnecessarily completely overlapped. By doing so, the process window ofthe second conductive column is increased, the alignment difficulty ofthe first conductive column and the second conductive column is reduced,the contact area of the first conductive column and the secondconductive column is increased, and then the resistance of the TSV isreduced, and the conductive performance of the TSV is improved.

In some embodiments, after S140, the method further includes: aninterconnection layer is formed on the device layer, and theinterconnection layer is electrically connected to the second conductivecolumn. The interconnection layer includes an interconnection throughhole and an interconnection metal layer. In an actual application,multiple stacked interconnection layers may be formed on the devicelayer. According to the stacking order of the interconnection layers,the interconnection layer closest to the device layer may be taken asthe first interconnection layer, and the interconnection layer on thefirst interconnection layer is taken as the second interconnectionlayer, and so on.

In another embodiment, after S140, the method further includes: abonding structure is provided, and the bonding structure includes asecond substrate and an interconnection layer formed on the secondsubstrate. The interconnection layer includes an interconnection throughhole and an interconnection metal layer, and the interconnection layeris bonded with the device layer. Herein, the interconnection layer iselectrically connected to the second conductive column. In an actualapplication, multiple stacked interconnection layers may be formed onthe second substrate. When bonding, the interconnection layer at theuppermost layer is bonded with the device layer. According to thestacking order of the interconnection layers, the interconnection layerclosest to the device layer may be taken as the first interconnectionlayer and the interconnection layer on the first interconnection layeris taken as the second interconnection layer, and so on.

In the embodiments of this application, the interconnection through holein the interconnection layer is electrically connected to the secondconductive column.

In the embodiments of this application, the device layer and theinterconnection layer are formed on different substrates, by doing so,the manufacturing processes for the device layer and the interconnectionlayer can be synchronously performed, so that the manufacturing time ofthe storage chip can be effectively shortened.

Further, the embodiments of this application provide a semiconductorstructure, which includes a substrate; a device layer, which is locatedat the front surface of the substrate; and a TSV, which is arranged inthe substrate and penetrates through the substrate and the device layer.FIG. 3 shows the semiconductor structure provided by the embodiments ofthe application. As shown in FIG. 3 , the semiconductor structureincludes a substrate 310; a device layer 320, which is located at thefront surface of the substrate 310; and a TSV.

The TSV is arranged in the substrate and penetrates through thesubstrate 310 and the device layer 320.

In the embodiments of this application, the device layer 320 includesthe storage array 321 and the contact structure 322.

In the embodiments of this application, the TSV includes the firstconductive column 331, which extends into the substrate from the backsurface of the substrate; the second conductive column 332, whichpenetrates through the device layer 320 and extends into the substratefrom the front surface of the substrate; and the conductive layer 3333,the first conductive column 331 and the second conductive column 332 areelectrically connected through the conductive layer 3333.

In the embodiments of this application, the TSV further includes atrench structure 333, which extends into the substrate from the backsurface of the substrate, and does not penetrate through the substrate310.

In the embodiments of this application, the trench structure includesthe first insulation layer 3331, the first diffusion barrier layer 3332,the copper thin film layer, the second diffusion barrier layer 3334 andthe insulation filling layer 3335. The copper thin film layer at thebottom of the trench structure 333 forms the conductive layer 3333.

It needs to be noted that the copper thin film layer may be formed atthe bottom of the trench only rather than the side wall of the trenchwhen forming the copper thin film layer. At this time, the copper thinfilm layer in the trench is the conductive layer.

In the embodiments of this application, the first conductive column 331penetrates through the insulation filling layer 3335 and the seconddiffusion barrier layer 3334, and is electrically connected to theconductive layer 3333.

In the embodiments of this application, the second conductive column 332penetrates through the first insulation layer 3331 and the firstdiffusion barrier layer 3332, and is electrically connected to theconductive layer 3333.

In the embodiments of this application, the first conductive column isformed in the trench structure, and the first conductive column iselectrically connected with the second conductive column through theconductive layer in the trench structure. In a direction parallel to thesubstrate, the width of the conductive layer is greater than that of thecontact surface of the first conductive column and the conductive layerand that of the contact surface of the second conductive column and theconductive layer, so that when the second conductive column is formed atthe front surface of the first substrate, it only needs to be flush withthe conductive layer. In other words, the projections of the firstconductive column and the second conductive column on the conductivelayer are not necessarily completely overlapped. By doing so, theprocess window of the second conductive column is increased, thealignment difficulty of the first conductive column and the secondconductive column is reduced, the contact area of the first conductivecolumn and the second conductive column is increased, and then theresistance of the TSV is reduced, and the conductive performance of theTSV is improved.

The above is only the specific implementation mode of this application,but the scope of protection of this application is not limited to.Person skilled in the art can easily think of changes or replacementswithin the scope of the technology disclosed in this application, whichshall be covered by the scope of protection of this application.Therefore, the scope of protection of this application should be subjectto the scope of protection of the appended claims.

It should be understood that term “one embodiment” or “an embodiment”mentioned in the whole specification intend to be included in at leastone embodiment this application in combination with the specificcharacteristics, structures, or characteristics of this embodiment.Therefore, term “in one embodiment” or “in an embodiment” in the wholespecification does not necessarily refer to the same embodiment. Inaddition, these features, structures, or characteristics may be combinedin one or more embodiments in any appropriate manner. It should beunderstood that in the various embodiments of this application, theserial number of the processes mentioned above does not imply the orderof execution, the order of execution of various processes shall bedetermined by its function and internal logic and shall not constituteany limitation on the implementation of the embodiments of thisapplication. The serial number of the embodiments of this application isonly for the purpose of description and does not represent the merits ofthe embodiments.

The methods disclosed in the several method embodiments provided by thisapplication may be arbitrarily combined without conflict to obtain newmethod embodiments.

The features disclosed in the several method embodiments provided bythis application may be arbitrarily combined without conflict to obtainnew product embodiments.

The several methods provided by the application or features disclosed inthe device embodiments may be arbitrarily combined without conflict toobtain new method embodiments or device embodiments.

The above is only the implementation mode of this application, but thescope of protection of this application is not limited to this. Thoseskilled in the art can easily think of changes or replacements withinthe scope of the technology disclosed in this application, which shallbe covered by the scope of protection of this application. Therefore,the scope of protection of this application should be subject to thescope of protection of the appended claims.

1. A method for forming a semiconductor structure, comprising: providinga first substrate; etching a back surface of the first substrate to forma trench; forming a conductive layer in the trench; forming a firstconductive column that extends into the trench at the back surface ofthe first substrate; forming a device layer at a front surface of thefirst substrate, the device layer comprising a storage array and acontact structure; and forming a second conductive column thatpenetrates through the device layer and extends into the firstsubstrate, the first conductive column being electrically connected withthe second conductive column through the conductive layer.
 2. The methodof claim 1, wherein said forming a conductive layer in the trenchcomprises: successively depositing a first insulation layer, a firstdiffusion barrier layer and a copper thin film layer in the trench, thecopper thin film layer located at bottom of the trench forming theconductive layer.
 3. The method of claim 2, wherein said forming a firstconductive column that extends into the trench at the back surface ofthe first substrate comprises: depositing a second diffusion barrierlayer in the trench, the second diffusion barrier layer covering thecopper thin film layer; filling an insulation material in the trench toform an insulation filling layer, the insulation filling layer coveringthe second diffusion barrier layer; forming a first blind hole byetching the insulation filling layer and the second diffusion barrierlayer, the first blind hole exposing part of the conductive layer;depositing a third diffusion barrier layer in the first blind hole, thethird diffusion barrier layer covering a side wall of the first blindhole and the exposed part of the conductive layer; and filling a firstmetal material in the first blind hole, the first metal materialcovering the third diffusion barrier layer.
 4. The method of claim 3,wherein before said forming a first blind hole, the method furthercomprises: forming a first photomask layer on a surface of theinsulation filling layer, etching the insulation filling layer and thesecond diffusion barrier layer by taking the first photomask layer thatis patterned as a mask to form the first blind hole.
 5. The method ofclaim 3, wherein an opening size of the trench is greater than anopening size of the first blind hole.
 6. The method of claim 3, whereinafter said filling a first metal material in the first blind hole, themethod further comprises: performing a chemical mechanical polishingprocess at the back surface of the first substrate, so that a topsurface of the first conductive column is flush with a top surface ofthe first substrate.
 7. The method of claim 3, wherein said forming asecond conductive column that penetrates through the device layer andextends into the first substrate comprises: forming a second blind holethat penetrates through the device layer and extends into the firstsubstrate by etching, the second blind hole exposing part of theconductive layer; depositing a second insulation layer in the secondblind hole, and removing the second insulation layer at bottom of thesecond blind hole by etching; and depositing a fourth diffusion barrierlayer and filling a second metal material in the second blind hole. 8.The method of claim 7, wherein before said forming a second blind hole,the method further comprises: forming a second photomask layer on asurface of the device layer, etching the device layer and the firstsubstrate by taking the second photomask layer that is patterned as amask to form the second blind hole.
 9. The method of claim 7, furthercomprising: performing a chemical mechanical polishing process at thefront surface of the first substrate, so that a top surface of thedevice layer is flush with a top surface of the second conductivecolumn.
 10. The method of claim 7, further comprising: forming aninterconnection layer on the device layer, the interconnection layerbeing electrically connected with the second conductive column, whereinthe interconnection layer comprises an interconnection through hole andan interconnection metal layer.
 11. The method of claim 7, furthercomprising: providing a bonding structure, the bonding structurecomprising a second substrate and an interconnection layer formed on thesecond substrate, wherein the interconnection layer comprises aninterconnection through hole and an interconnection metal layer; andbonding the interconnection layer and the device layer.
 12. The methodof claim 11, wherein the interconnection layer is electrically connectedwith the second conductive column.
 13. A semiconductor structure,comprising: a substrate; a device layer that is located at a frontsurface of the substrate; and a through-silicon via (TSV) that isarranged in the substrate and penetrates through the substrate and thedevice layer.
 14. The semiconductor structure of claim 13, wherein thedevice layer comprises a storage array and a contact structure.
 15. Thesemiconductor structure of claim 13, wherein the TSV comprises: a firstconductive column that extends into the substrate from a back surface ofthe substrate; a second conductive column that penetrates through thedevice layer and extends into the substrate from a front surface of thesubstrate; and a conductive layer, the first conductive column and thesecond conductive column are electrically connected through theconductive layer.
 16. The semiconductor structure of claim 15, whereinthe TSV further comprises a trench structure that extends into thesubstrate from the back surface of the substrate and does not penetratethrough the substrate.
 17. The semiconductor structure of claim 16,wherein the trench structure comprises a first insulation layer, a firstdiffusion barrier layer, a copper thin film layer, a second diffusionbarrier layer and an insulation filling layer; wherein the copper thinfilm layer located at a bottom of the trench structure forms theconductive layer.
 18. The semiconductor structure of claim 17, whereinthe first conductive column penetrates through the insulation fillinglayer and the second diffusion barrier layer, and is electricallyconnected with the conductive layer.
 19. The semiconductor structure ofclaim 18, wherein the second conductive column penetrates through thefirst insulation layer and the first diffusion barrier layer, and iselectrically connected with the conductive layer.